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MAX2769
Universal GPS Receiver
011
01
010
001
00
000
-7
-6
-5
-4
-3
-2
-1
100
1
2
3
4
5
6
7
10
101
110
11
111
Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases
MSB is output at I1, the second bit is at I0, and the LSB
is at Q1.
Figure 2 illustrates the ADC quantization levels for 2-
and 3-bit cases and also describes the sign/magnitude
data mapping. The variable T = 1 designates the loca-
tion of the magnitude threshold for the 2-bit case.
Fractional Clock Divider
A 12-bit fractional clock divider is located in the clock
path prior to the ADC and can be used to generate the
ADC clock that is a fraction of the reference input
clock. In a fractional divider mode, the instantaneous
division ratio alternates between integer division ratios
to achieve the required fraction. For example, if the
fractional output clock is 4.5 times slower than the input
clock, an average division ratio of 4.5 is achieved
through an equal series of alternating divide-by-4 and
Maxim Integrated
T=1
divide-by-5 periods. The fractional division ratio is
given by:
f OUT / f IN = L COUNT / (4096 - M COUNT + L COUNT )
where L COUNT and M COUNT are the 12-bit counter val-
ues programmed through the serial interface.
DSP Interface
GPS data is output from the ADC as the four logic sig-
nals (bit 0 , bit 1 , bit 2 , and bit 3 ) that represent sign/magni-
tude, unsigned binary, or two’s complement binary data
in the I (bit 0 and bit 1 ) and Q (bit 2 and bit 3 ) channels. The
resolution of the ADC can be set up to 3 bits per chan-
nel. For example, the 2-bit I and Q data in sign/magni-
tude format is mapped as follows: bit 0 = I SIGN , bit 1 =
I MAG , bit 2 = Q SIGN , and bit 3 = Q MAG . The data can be
serialized in 16-bit segments of bit 0 , followed by bit 1 ,
bit 2 , and bit 3 . The number of bits to be serialized is con-
trolled by the bits STRMBITS in the Configuration 3 regis-
13
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